1. Field of the Invention
The invention pertains to fabricating semiconductor structures, and more particularly to nickel silicide on a silicon semiconductor device wherein the nickel silicide is formed from a ternary metal alloy film.
2. Description of the Related Art
Modern semiconductor technology requires the utilization of low resistance materials in the active regions of metal-oxide-semiconductor field effect transistors (MOSFETs) and other devices. To satisfy the low-resistance requirements for source/drain and gate regions, self-aligned silicide that is simultaneously formed on the source/drain and gate regions has been widely used in the manufacturing of large-scale integrated silicon circuits.
The most common currently used materials for creating a silicide layer are titanium or cobalt. However, these silicide materials face numerous process-integration difficulties and drawbacks for future generations of semiconductor structures or devices which will feature ultra narrow lines as well as ultra shallow junctions.
For example, an unacceptably high sheet resistance results when TiSi2 is formed on narrow (sub-0.1 μm) gate lines (due to the lack of nucleation centers for the transition from the undesirable C49 phase to the low resistivity C54 phase), and this high resistance presents a major drawback for this silicide material. On the other hand, CoSi2 suffers from other drawbacks associated with aggressive vertical scaling, and these drawbacks include severe junction leakage, a relatively large consumption of silicon and difficulty in achieving a CoSi2 layer having uniform thickness. These drawbacks limit the use of CoSi2 in ultra-shallow junction devices.
Nickel monosilicide (NiSi) represents a suitable low resistivity candidate for use in future generations of silicon complementary metal oxide semiconductor (CMOS) devices. The distinct advantages of NiSi include low electrical resistivity, low Si consumption for its formation, and an ability to maintain low resistivity even at narrow line widths (sub-0.1 μm). The full implementation of NiSi in future generations of silicon semiconductor structures and devices, however, depends on the resolution of several process-integration issues.
The formation of quality NiSi crucially depends on the cleanliness of the substrate's Si surface as well as the pureness of the ambient annealing environment during thermal annealing. Any presence of residual native silicon oxide on the original silicon surface, or oxygen in the ambient annealing environment, tends to degrade the quality of the NiSi and may even cause the complete failure of NiSi formation (if the original silicon surface is covered by a continuous silicon oxide). In a manufacturing environment, the presence of native oxide represents the major hindrance to forming such a high quality NiSi layer.
For example, device wafers on the production line for Ni deposition may encounter delays. These delays allow for the growth of native oxide on the Si surface. If the growth of native oxide is substantial, it will act as a diffusion barrier for Ni, thereby preventing the diffusion of Ni into the silicon to form NiSi. Also, a partial growth of native oxide on localized areas of the Si surface will lead to non-uniform growth of NiSi, resulting in rough interfaces and consequent high diode leakage on ultra-shallow junction devices.
In addition, NiSi is not thermally stable at relatively high processing temperatures. For thin NiSi films, severe agglomeration (or NiSi island formation) normally begins to occur at 600° C., while the transformation of NiSi to NiSi2 takes place at 700° C. Both NiSi agglomeration and NiSi-to-NiSi2 transformation degrade the electrical properties of nickel silicide films and cause leakage problems in silicided shallow junctions.
Related art technologies have attempted to address the deficiencies of semiconductor devices incorporating NiSi films. These related art technologies are typified by U.S. Pat. No. 6,339,021 (titled “Methods for effective nickel silicide formation”), which describes a method of forming a NiSi layer on a semiconductor structure or device in the presence of native oxide. This method includes at least the following three embodiments: 1) providing a thin Ti capping layer over an underlying Ni layer; 2) providing a TiN layer over a Ti capping layer which is over a Ni layer, in order to free all the Ti atoms in the Ti capping layer for reaction with the underlying native oxide at the Ni—Si interface; and 3) providing a monolayer of Ti sandwiched between the native oxide and Ni. In each of these embodiments, the Ti is made mobile to react with and to reduce the native chemical oxide layer when the substrate is annealed at 600° C. and to transform the Ni into NiSi.
Another approach to the NiSi problem is typified by U.S. Pat. No. 6,531,396 (titled, “Method of fabricating a nickel/platinum monosilicide film”), which describes a method of forming a NiSi layer on a semiconductor structure or device by incorporating a small amount of Pt (5 at. %) into Ni to increase the NiSi2 nucleation temperature and NiSi agglomeration temperature.
This mono-metal doping approach was also tried in PCT Application no. PCT/SG03/00096 (titled, “Method for forming a nickel silicide later on a silicon substrate”). This application describes a method of forming a NiSi layer on a semiconductor structure or device that has a layer of native oxide on the Si substrate without an increase in silicidation reaction temperature by incorporating a small amount of Ti (5 at. %). The Ti atoms reduce the interfacial oxide to provide a diffusion membrane facilitating the influx of Ni into Si substrate to form NiSi.
The above-described technologies seek to solve the particular process-integration issues that are experienced in established methods for implementation in future generations of semiconductor structures or devices. That is, NiPt specifically addresses NiSi2 nucleation and NiSi agglomeration, and NiTi specifically addresses NiSi sensitivity to interfacial oxides. However, distinct disadvantages of the above-described technologies arise from their inability to solve the two process-integration problems described above (non-uniform growth and thermal instability), which are the most probable concurrently occurring problems associated with the NiSi process. As a result, there is a need for an effective technology that will permit the utilization of NiSi in very small submicron line width semiconductor devices.